The present invention relates to a semiconductor manufacturing technology and, more particularly, an effective technology applied to miniaturization of semiconductor devices.
In a semiconductor device accommodating semiconductor chips each including a semiconductor device, a stack structure is known as a typical structure for accommodating the semiconductor chips in one package.
In a semiconductor device having a stack structure, semiconductor chips are stacked into a 2-layer structure formed in a resin mold to create a package.
A semiconductor device and a method for fabricating the package are described in documents such as Japanese Unexamined Patent Publication No. 2000-188369, Japanese Unexamined Patent Publication No. 2000-299431 and Japanese Unexamined Patent Publication No. Hei11(1999)-219984. As disclosed in Japanese Unexamined Patent Publication No. 2000-188369, in a structure wherein another chip is mounted by stacking the chip on a chip mounted in a phase-up-mounting process and connected in a wire-bonding process, it is necessary to stack the upper chip on the lower chip in such a way that electrodes provided on the lower chip are not covered by the upper chip. Thus, there are many constraints imposed on the chip size.
As opposed to Japanese Unexamined Patent Publication No. 2000-299369, in Japanese Unexamined Patent Publication No. 2000-299431 and Japanese Unexamined Patent Publication No. Hei 11(1999)-219984, there is disclosed a structure wherein a lower-layer semiconductor chip is connected as a flip chip in a phase-down mounting process whereas an upper-layer semiconductor chip is mounted in a phase-up-mounting process and connected in a wire-bonding process, so that there are no constraints imposed on the chip size as described above and the structure has a high degree of freedom.
That is, Japanese Unexamined Patent Publication No. 2000-299431 discloses a technology for improving a wire-bonding characteristic of an upper-layer chip in a semiconductor device having a structure in which a portion of the upper-layer chip is protruding.
In addition, Japanese Unexamined Patent Publication No. Hei11(1999)-219984 discloses a semiconductor-device package having a chip stacked-layer structure and allowing an SMT (Surface Mount Technology) to be used for mounting a semiconductor chip on a thick-film wiring substrate as well as discloses a method for fabricating the semiconductor-device package.